1. Field of the Invention
The present invention relates generally to synchronization devices and, more particularly, to reducing the lock time of devices implementing a phase locked loop to synchronize input signals.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
During high frequency operation, it is often desirable to synchronize the timing of certain signals, such as clock signals, with other clock signals or data signals. Various synchronization devices may be implemented to provide an output signal that is matched in terms of phase and/or frequency to an input signal, which may be an external clock signal, for example. Synchronization devices may, for example, be implemented to synchronize an external system clock with data being transmitted from a memory device.
One means of synchronizing signals is by implementing a delay locked loop (DLL) circuit. The DLL circuit is used to create an output signal that is phase-matched to the input signal. In conventional DLL circuits, an input buffer is used to receive an input signal, such as an external clock signal, and to transmit the signal to one or more delay lines. The delay line includes a number of delay elements. A phase detector may be used to compare the input clock signal to the output signal by using a feedback loop. The information can then be fed from the phase detector to a shift register to move through the delay elements in the delay line incrementally to search for a match. When the input signal and output signal are equal or “matched”, the signals are synchronized, and the DLL is considered locked. As can be appreciated, the output signal inherently has the same frequency as the input clock signal.
While DLLs may be desirable for pure delay compensation or clock conditioning applications based on the unconditional stability of the DLL architecture, for other applications, such as frequency synthesis, other delay devices may be desirable. One such device is the phase locked loop (PLL). The fundamental difference between the PLL and the DLL is that instead of a delay line, the PLL implements a voltage controlled oscillator (VCO) to generate a clock signal that approximates an input clock signal. In addition to providing a mechanism for phase adjustment, as with the DLL, the PLL provides a mechanism for frequency adjustment and matching.
Generally, a PLL is a synchronization device which implements a voltage-controlled oscillator (VCO). The VCO is constantly adjusted under the control of a phase detector to match the phase and frequency of an input signal. In addition to stabilizing a particular communications channel (i.e., maintaining the frequency), a PLL may be implemented to generate a signal, modulate or demodulate a signal, reconstitute a signal with less noise, or multiply/divide a frequency. PLLs are often used in wireless communication, particularly where signals are carried using frequency modulation (FM) or phase modulation (PM). PLLs are more commonly used for digital data transmission, but can also be designed for analog information.
Specifically, a PLL includes a VCO that is tuned using a varactor. The PLL includes a phase/frequency detector which causes the VCO to seek and lock onto the desired frequency, based on the output of a crystal-controlled reference oscillator. As with the DLL, the PLL is implemented through a feedback scheme. If the VCO frequency departs from the selected crystal reference frequency, the phase comparator produces an error voltage that is applied to the varactor, bringing the VCO back to the reference frequency. The PLL, VCO, reference oscillator and phase comparator form a frequency synthesizer.
Disadvantageously, using a PLL to synchronize signals often requires several hundred clock cycles to lock both the phase and frequency of a reference signal. By delaying the signal lock, system performance may be degraded. Thus, it would be desirable to provide a synchronization device that locks both phase and frequency in a minimum number of clock cycles.
Embodiments of the present invention may address one or more of the problems set forth above.